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NXP Semiconductors /LPC15xx /INMUX /SCT1_INMUX[5]

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Interpret as SCT1_INMUX[5]

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INP_N0RESERVED

Description

Pinmux register for SCT1 input 0

Fields

INP_N

Input number (decimal value) to SCT1 inputs 0 to 6. 0 = PIO0_15 (external pin) 1 = PIO0_16 (external pin) 2 = PIO0_21 (external pin) 3 = PIO0_31 (external pin) 4 = PIO1_4 (external pin) 5 = PIO1_5 (external pin) 6 = PIO1_15 (external pin) 7 = PIO1_16 (external pin) 8 = SCT0_OUT4 (large SCT0 output 4) 9 = SCT3_OUT4 (small companion SCT3 output 4) 10 = SCT3_OUT5 (small companion SCT3 output 5) 11 = ADC0_THCMP_IRQ 12 = ADC1_THCMP_IRQ 13 = COMP0_OUT (One output from each analog comparator) 14 = COMP1_OUT 15 = COMP2_OUT 16 = A COMP3_OUT 17 = SCTIPU_ABORT 18 = SCTIPU_SAMPLE0 19 = SCTIPU_SAMPLE1 20 = SCTIPU_SAMPLE2 21 = SCTIPU_SAMPLE3 22 = DEBUG_HALTED DEBUG_HALTED (from ARM Cortex CoreSight Debugger)
RESERVED

Reserved.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data